1. Field of the Invention
This disclosure relates to manufacturing techniques for semiconductor devices, and more particularly, to a method of fabricating a gate of a fin type transistor.
2. Description of the Related Art
Semiconductor devices are becoming more highly integrated and can be operated at lower power and at higher speed. Particularly, methods have been developed to prevent a short channel effect and improve device reliability. A fin type transistor such as FinFET (Fin Field Effect Transistor) formed using such a method has been introduced to enhance a current characteristic.
A fin type transistor includes a fin type active region. Both sidewalls of the fin type active region can be used as channels, and thus, the current flowing into the channels can be substantially increased.
One exemplary method used to expose the sidewalls of the fin type active region is a FinFET fabrication method implemented with a damascene process. In more detail, device isolation regions defining active regions are formed and then portions of the device isolation regions are recessed to expose the sidewalls of the active regions.
However, when the recesses that expose the sidewalls of the active regions are formed in the device isolation regions, various etching and cleaning processes are generally required. The various etching and cleaning processes can include etching and cleaning processes performed with respect to silicon oxide. Hence, it is often very difficult to prevent etch damage to the silicon oxide layer in the device isolation regions, for example, which mainly includes a silicon oxide layer. As a result, it is also difficult to precisely control the widths of the recesses.
Gate lines are filled in the recesses formed in the device isolation regions so that gates are disposed on the sidewalls of the active regions. However, if the widths of the recesses are larger than the initially determined widths of the recesses, a bridge may be formed between the gate lines, resulting in defective device operation.
Accordingly, a method to be used to precisely control the widths of recesses and form the recesses exposing sidewalls of active regions defined by device isolation regions is needed. Since the device isolation regions mainly include a silicon oxide layer, a special development of a process and/or etch conditions is required to prevent undesirable etch loss and cleaning loss caused by the silicon oxide layer.
Embodiments of the invention address these and other disadvantages of the conventional art.